Testing of systems on a chip is essentially for quality assurance. As systems have become more complex and faster, effective testing has become more difficult and more expensive. Generally, testing involves using external testers to analyze data exchanges with an external memory. Unfortunately, because of the increasing disparity between tester speeds and double data rate (DDR) memory exchanges, existing techniques fail to provide the desired quality assurance.
Stretch mode, one traditional technique in which the data strobe time is stretched with a ratio equivalent to the speed ratio of the DDR to the tester speed, become entirely impractical as speeds increase. The testing interface has a much slower speed than is desired, often with a stretch factor of four or more. As the stretch factor increases, so does the command bubble duration. The logic to handle the DDR input/output (I/O) is both complex and intrusive. Moreover, for stretch mode to work for design for manufacturability (DFX) tests, enormous tuning of the tester is required. Such tuning has been found impractical to real-world applications.
A second historical testing option is write data always response (WDAR) mode. This mechanism requires 128 cache lines of additional memory for data. Often, this amount of memory does not exist in products to be tested. Moreover, WDAR has a huge time impact resulting from the need to fill the memory with known data before starting the test. Finally, it is not possible to calculate the expected response on the fly. Therefore, the WDAR test writer must perform pre-silicon simulation and compare with post-silicon results. Often, mismatches occur between the signatures calculated from the simulation and those that exist in the actual silicon.